1. Field of the Invention:
The present invention relates to a method and to an apparatus for investigating the latch-up propagation in CMOS circuits by documenting the infrared radiation emitted by the circuit in response to latch-up conditions.
2. Description of the Prior Art
Parasitic thyristor structures always exist in integrated CMOS circuits and triggering thereof can lead to a destruction of the component as a consequence of the heating of the current paths that thereby occurs. Fundamentally, this effect referred to as latch-up can be recognized on the basis of the discontinuous rise and the locking of the supply current without, however, being able to identify the affected circuit parts and improve them by modifying the design or with technological measures (higher well and substrate dopings, utilization of a low-impedance epitaxial layer, etc.). A series of method for localizing latch-up-sensitive regions in integrated CMOS circuits have therefore been developed (see, for example, Otto, et al, "Schaltungsanalyse in ICs mit dem Rasterlasermikroskop", VDI Berichte, No. 659,1987, pp. 381-393; R. Muller, "Scanning Laser Microscope for Inspection of Microelectronic Devices", Siemens Forschungs-und Entwicklungsberichte, Vol. 13, No. 1, 1984, pp. 9-14; and N. Khurana, "Pulsed Infra-Red Microscopy for Debugging Latch-Up on CMOS Products", IEEE/IRPS, International Reliability Physics Symposium 1984, pp. 122-127). The method disclosed by Khurana in the IEEE/IRPS article thereby particularly offers the advantage that the primary latch-up centers that cannot be localized with conventional liquid crystal techniques can also be identified.